Vehicle having a sensor with capacitor on chip

ABSTRACT

A vehicle includes a magnetic sensor comprising a plurality of layers including a substrate having circuitry, at least one conductive layer to interconnect the circuitry, and an insulator layer to electrically insulate the at least one conductive layer. First and second conductive layers are generally parallel to the substrate with a dielectric layer disposed between the first and second conductive layers such that the first and second conductive layers and the dielectric layer form a capacitor. A first terminal is electrically connected to the first conductive layer and a second terminal is electrically connected to the second conductive layer.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a Divisional application of U.S. patent applicationSer. No. 11/279,780 filed on Apr. 14, 2006, which is hereby incorporatedherein by reference in its entirety.

STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH

Not Applicable.

BACKGROUND

As is known in the art, there are a variety of sensors that are usefulfor particular applications. For example, magnetic sensors are useful todetect movement, such as rotation, of an object of interest. Typically,Hall-effect sensors require a discrete decoupling capacitor componentplaced on or near the sensor to enhance EMC (ElectromagneticCompatibility) and reduce so-called long-wire noise problems. However,external capacitors incur added cost and processing at the individualdevice level. External capacitors also increase the total package sizeif the capacitor resides on the leadframe or requires an additionalprinted circuit board.

SUMMARY

The present invention provides a magnetic sensor including an on chipcapacitor formed from first and second conductive layers and adielectric layer disposed over a substrate. With this arrangement, theneed for an external decoupling capacitor may be eliminated. While theinvention is primarily shown and described in conjunction withparticular layer stack ups, devices and configurations, it is understoodthat the invention is applicable to circuits in general in which it isdesirable to provide a capacitive impedance.

In one aspect of the invention, a magnetic sensor comprises a pluralityof layers including a substrate including circuitry, at least oneconductive layer to interconnect the circuitry, and an insulator layerto electrically insulate the at least one conductive layer. First andsecond conductive layers are disposed above the substrate, and adielectric layer is disposed between the first and second conductivelayers such that the first and second conductive layers and thedielectric layer form a capacitor. The sensor further includes a firstterminal electrically connected to the first conductive layer and asecond terminal electrically connected to the second conductive layer.

In another aspect of the invention, a method includes forming a firstconductive layer over a substrate containing circuitry, forming adielectric layer over the first conductive layer, and, forming a secondconductive layer over the dielectric layer such that the firstconductive layer, the dielectric layer, and the second conductive layerform a first capacitor. A first terminal can be coupled to the firstconductive layer and a second terminal can be coupled to the secondconductive layer.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing features of this invention, as well as the inventionitself, may be more fully understood from the following description ofthe drawings in which:

FIG. 1A is a top view of a sensor having an on chip capacitor inaccordance with an exemplary embodiment of the invention;

FIG. 1B is a cross-sectional view of the sensor of FIG. 1A taken alongline A-A;

FIGS. 2A and 2B show a two-wire magnetic sensor having an on chipcapacitor;

FIG. 3 is a pictorial top view of a three-wire magnetic sensor having anon chip capacitor;

FIG. 4 is a schematic diagram of a sensor having multiple on chipcapacitors; and

FIG. 5 is a flow diagram showing an exemplary sequence of steps tofabricate a sensor having an on chip capacitor.

DETAILED DESCRIPTION

FIGS. 1A-B show an exemplary embodiment of a magnetic sensor 100embodiment having an on chip capacitor 102 in accordance with thepresent invention. In the illustrated embodiment, the sensor 100 is atwo-wire Hall effect type sensor having a VCC terminal 104 and a groundterminal 106. The capacitor 102 can be provided as a decouplingcapacitor coupled between the VCC terminal 104 and the ground terminal106, for example. As described more fully below, the capacitor 102 canbe coupled to a VCC cap terminal 108, which is at the same potential asthe VCC terminal 104 in an exemplary embodiment. The VCC cap terminal108 and the VCC terminal 104 can be electrically coupled using anysuitable technique, such as wire bonding. This arrangement allowsbreakdown testing. In alternative embodiments, Vcc and Vcc cap bond padscould be combined to form a single pad.

A first metal layer 116 is disposed on the substrate 116 and an optionalsecond layer 118, which is sandwiched between first and secondinsulating layers 120, 122, is disposed over the first metal layer 116.The first and second metal layers 116, 118 provide, for example,interconnection and routing for the device layer 112. The first andsecond insulating layers 120, 122 can be provided, for example, asinterlayer dielectric and/or passivation layers.

First and second conductive layers 124, 126 are separated by adielectric material 128 to form the on chip capacitor 102 above thesubstrate. The capacitor 102 is covered by a further insulating layer130. In an exemplary embodiment, the capacitor 102 is separated, andelectrically isolated, from the second metal layer 118 by the secondinsulating layer 122.

In an exemplary embodiment, a substrate 110, e.g., silicon, includes anintegrated circuit (IC) in layers 112, 116, 120, 118, and/or 122 inwhich circuitry is formed in a manner well known to one of ordinaryskill in the art. The device layer 112 can include a Hall element 114that forms part of the magnetic sensor 100. The device layer may includevarious layers necessary to form an integrated circuit, including, butnot limited to, implant or doped layers, polysilicon, epi layers, oxide,or nitride layers.

While a particular layer stack up is shown and described, it isunderstood that other embodiments having different layering orders andgreater and fewer metal and other layers are within the scope of theinvention. In addition, additional conductive layers can be added toform additional capacitors to meet the needs of a particularapplication.

As shown in FIG. 2A, for the illustrated two-wire sensor, a senseresistor Rsense can be coupled between the ground terminal 106 and aground connection, or as shown in FIG. 2B, the sense resistor Rsense canbe coupled between the VCC terminal 104 and the power supply. Thisenables measurement of the sensor 100 output in the form of currentchanges in response to a positional displacement of a magnetic object ofinterest. By providing an on chip capacitor, the need for an externaldecoupling capacitor for the sensor may be eliminated.

In another embodiment shown in FIG. 3, a three-wire magnetic sensor 200includes an on chip capacitor 202 with a Vout terminal 204 to provide asensor output signal. The sensor 200 of FIG. 3 has some similarity withthe sensor 100 of FIGS. 1A-1C, where like reference numbers indicatelike elements.

It is understood that higher breakdown voltage requirements for thecapacitor may limit the amount of capacitance that can be provided bythe on chip capacitor. Lower breakdown voltage requirements may increasethe amount of capacitance that can be provided. Factors that determinethe characteristics of the on chip capacitor 102 include, for example,die size, metal layer area, conductive layer area, dielectric material,selected breakdown voltage, layer spacing, geometry, and others.

A variety of dielectric materials for the capacitor 166 can be usedincluding, but not limited to; silicon nitride, silicon oxide, e.g.silicon dioxide, Tantalum oxide, Aluminum oxide, ceramics, glass, mica,polyesters (eg. Mylar), KAPTON, polyimides (e.g. Pyralin by HDMicrosystems), benzocyclobutene (BCB, e.g. Cyclotene by Dow Chemical),and polynorbornene (e.g., Avatrel by Promerus). Inorganic dielectricsmay be preferable for some applications based on their higher dielectricconstant and the ability to create uniform thin films in the sub-micronrange; e.g. 3,000 to 5,000 Angstroms in thickness.

These same dielectrics may be used where appropriate for interlayerdielectric, or final passivation materials. In the case of theinterlayer dielectric, it may be advantageous to select a material thatplanarizes well, and has a low dielectric constant for use between thesecond metal layer 118 and the conductive layer 124. This should reduceany unwanted coupling of signals from lines on the metal layer 118 tothe conductive layer 124, which may, for example, be a ground plane.

A variety of suitable materials can be used to provide the device layerfor the sensor including silicon, gallium arsenide, silicon on insulator(SOI), and the like. In addition, various materials can be used toprovide the metal layers and the conductive layers, which form thecapacitor. Exemplary metal and conductive layer materials includecopper, aluminum, alloys and/or other suitable metals.

In general, for a die size of about 2.5 to 3 mm², the on chip capacitorprovides in the order of 400 pF. For a larger die, e.g., about 5 mm²,the capacitor provides in the order of 800 pF. In exemplary embodiments,the capacitor provides a capacitance from about 100 pF to about 1,500 pFfor a substrate ranging in size from about 1 mm² to about 10 mm².

In one particular embodiment, the first and second conductive layers124, 126 (FIG. 1B) have dimensions of 2.3 mm². The dielectric materialis silicon nitride having a thickness ranging of approximately 3,000 Åto about 5,000 Å. This arrangement provides a breakdown voltage of aboutat least 50V with a capacitance of about 300 pF to about 500 pF.

A Hall sensor having an on chip capacitor of about 100 pF to about 1,500pF and at least 50V breakdown voltage is well suited for many vehicleapplications, such as anti-lock brake sensors (ABS), linear positionsensors, angle sensors, transmission sensors, cam sensors, and cranksensors.

In general, the first and second conductive layers 124, 126 (FIG. 1B)forming the capacitor 102 cover from about thirty percent to aboutninety percent of the die area. The capacitor 102 may be above the diewhere above refers to some degree of overlap between generally parallelplanes formed by the die and the conductive layers of the capacitor.

In one embodiment, the first and second layers cover an area of abouteighty percent of the die area. Such a capacitor would provide acapacitance on the order of 400 pF, which can provide additional EMCprotection to the circuitry on the die. In some devices, in the order of200 pF may be sufficient for EMC or long-wire protection. In such a casethe area required by the capacitor is not as large, and may be on theorder of fifty percent of the total die area. In general, the capacitorcan be sized to meet the needs of a particular application.

As used herein, the term die refers to a substrate, which may be asemiconductor or a semiconductor layer on an insulator, for example SOIsubstrates, with its associated circuits or electronic device elements.The circuits on the die may include semiconductor devices, for examplediodes, and transistors, and passive devices, for example a resistor,inductor, or capacitor.

As shown in FIG. 4, the second conductive layer 304 can be separated toform multiple capacitors, shown as first and second capacitors 306, 308provided the first conductive layer 302 is at the same potential forboth. It would also be apparent that the first conductive layer 302could also be split to form separate capacitors, although it may requirethe addition of a bonding pad depending on the application. The firstcapacitor 306 provides a decoupling capacitor between the VCC capterminal 108 and ground 106. The second capacitor 308 is coupled betweena Vout cap terminal 310 and ground 106. A Vout terminal 204, which canbe coupled to the Vout cap terminal 310 via wire-bond, provides a sensoroutput signal for a three-wire magnetic sensor, for example.

It is understood that the apportionment of the first and secondconductive layers 302, 304 can be made to achieve capacitancerequirements for a particular application. In addition, the first andsecond conductive layers can be split to form any practical number ofcapacitors above the die. Such multiple capacitor configurations may beuseful for applications that require more than two-wires; for example athree-wire part with power, ground, and independent output pins.

FIG. 5 shows an exemplary sequence of steps to fabricate a sensor havingan on-chip capacitor. In general, fabrication of the integratedcapacitor is performed after an integrated circuit process is performed,which may also be referred to as the base process.

In step 400, first and second metal layers are formed over a substrate.In one particular embodiment, the base process includes two metal layersfor interconnection and routing and a final passivation. It may bedesirable to change the final passivation on the base process, which maytypically include an oxide and nitride layer. After the second metallayer, in step 402 an interlayer dielectric is deposited. Again, this isthe place where the final passivation would be performed in the baseprocess. The interlayer dielectric can be an oxide, nitride, or organicdielectric such as a polyimide, or BCB. A material such as BCB hasadvantages in that it planarizes the underlying substrate well andallows a flat surface for the subsequent capacitor deposition. In step404, the interlayer dielectric is then patterned to open connections tothe bond pads in the underlying integrated circuit.

In step 406, a conductive layer is then deposited on the wafer andpatterned to form one of the capacitor electrodes. In the illustratedembodiment, the lower capacitor electrode is connected to the groundbonding pad, but not any other portions of the underlying circuit. Insome cases it may be desirable to have the lower capacitor layer on theother bonding pads of the integrated circuit, although these pads arenot connected to the capacitor electrode. In step 408, the capacitordielectric is deposited and patterned. The dielectric material may besilicon nitride, or other suitable material. In step 410, the secondconductive layer of the capacitor is deposited on the wafer andpatterned to form the top electrode of the capacitor. The upper layer ofthe capacitor may be connected to the Vcc pad of the integrated circuit,or it may be its own bonding pad. Having the upper layer of thecapacitor as an independent pad allows the dielectric breakdown to betested during the final test of the integrated circuit with an on-chipcapacitor. In step 412, a final passivation layer is applied to theintegrated circuit with the capacitor and pattern openings for thebonding pads.

It is understood that a variety of suitable fabrication processes can beused to form a sensor having an on chip capacitor including, but notlimited to, bipolar, DMOS, bi-CMOS, CMOS, and processes and combinationsof these and other processes

While exemplary embodiments contained herein discuss the use of a Halleffect sensor, it would be apparent to one of ordinary skill in the artthat other types of magnetic field sensors may also be used in place ofor in combination with a Hall element. For example the device could usean anisotropic magnetoresistance (AMR) sensor and/or a GiantMagnetoresistance (GMR) sensor. In the case of GMR sensors, the GMRelement is intended to cover the range of sensors comprised of multiplematerial stacks, for example: linear spin valves, a tunnelingmagnetoresistance (TMR), or a colossal magnetoresistance (CMR) sensor.In other embodiments, the sensor includes a back bias magnet.

Having described exemplary embodiments of the invention, it will nowbecome apparent to one of ordinary skill in the art that otherembodiments incorporating their concepts may also be used. Theembodiments contained herein should not be limited to disclosedembodiments but rather should be limited only by the spirit and scope ofthe appended claims. All publications and references cited herein areexpressly incorporated herein by reference in their entirety.

1. A vehicle, comprising: a sensor, comprising: a substrate includingcircuitry; at least one conductive layer to interconnect the circuitry;an insulator layer to electrically insulate the at least one conductivelayer; first and second conductive layers generally parallel to thesubstrate; a dielectric layer disposed between the first and secondconductive layers such that the first and second conductive layers andthe dielectric layer form a capacitor; and first and second terminals,wherein the first terminal is electrically connected to the firstconductive layer and the second terminal is electrically connected tothe second conductive layer.
 2. The vehicle according to claim 1,wherein the capacitor overlaps with at least thirty percent of an areaof the substrate.
 3. The vehicle according to claim 1, wherein the firstand second conductive layers are divided to form a further capacitor. 4.The vehicle according to claim 1, wherein the capacitor provides acapacitance from about 100 pF to about 1,500 pF for a substrate rangingin size from about 1 mm² to about 10 mm².
 5. The vehicle according toclaim 1, wherein the sensor includes a Hall sensor.
 6. The vehicleaccording to claim 5, wherein the Hall sensor is a two-wire Hall sensor.7. The vehicle according to claim 1, wherein the first terminal isadapted for coupling to a voltage supply terminal.
 8. The vehicleaccording to claim 7, wherein the second terminal is adapted forcoupling to a ground terminal.
 9. The vehicle according to claim 1,wherein the sensor includes a back bias magnet.
 10. The vehicleaccording to claim 1, wherein the sensor includes an AMR sensor.
 11. Thevehicle according to claim 1, wherein the sensor includes a GMR sensor.